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SC5864D
Audio Processing SoC With High-Performance DSP
The SC5864D is a highly-integrated audio system-on-chip (SoC) integrated with Cortex-M0 processor for low power management, and a high performance audio dedicated DSP for sound effect processing. Furthermore, it is also integrated with SAR-ADC, USB, SD/MMC controllers, and audio CODEC.
Main feature
Architecture
  • DSP
  • 5-level pipelines, maximum operating frequency: 160MHz;
  • 32bit/16bit multiplication: MAC16, MUL16, MUL32;
  • 32bit integer division;
  • Single-precision floating-point operation;
  • Dedicated hardware audio acceleration engine;
  • 32KB instruction/data Cache, WB/WT supported;
  • Local SRAM;
  • MCU
  • High performance Cortex-M0 core, maximum operating frequency: 80MHz;
  • Embedded 8KB Cache, four address areas, independently configure;
  • Supports frequency reduction, a quarter of maximum bus frequency;
Clock & Power Manager
  • External 12MHz oscillators;
  • Built-in RCL and RCH;
  • Built-in System PLL, Audio PLL and USB PLL;
  • Built-in double 1.2V LDO;
  • Multi low-power operating modes supported, such as frequency reduction, STOP mode. 
Memory Controller
  • SPI flash controller
  • Supports SPI Flash 1/2/4-wire modes;
  • Core runs directly in SPI Flash;
  • Packaged with 16Mbit SPI Nor Flash;
  • SRAM
  • Embedded 240KB SRAM, system 32KB+16KB, DSP 192KB;
  • Supports Byte, Half-word, Word access;
Peripherals
  • Audio CODEC
  • Built-in stereo Audio ADCs; SNR 100db (A-weight, Line in);
  • Supports stereo analog MIC input and ALC;
  • Built-in stereo Audio DAC, SNR 100db(A-weight, Line out);
  • USB_HS
  • Built-in USB2.0 high-speed PHY;
  • Compliance with USB2.0 standard;
  • Supports control, bulk, interrupt, and synchronous transfer;
  • Built-in 2KB SRAM;
  • Built-in Normal and Scatter-Gather DMA transfer;
  • SD/MMC
  • Compliance with SD2.0, MMC4.3 standards;
  • Supports 4-bit mode;
  • Built-in Normal and chained DMA transfer;
  • UARTx3
  • 3 UART modules provided;
  • High-speed UART1 integrated with 64-byte FIFO, UART2 with 8-byte FIFO, while UART3 with 16-byte FIFO;
  • Programmable data bits and stop bit;
  • Parity check supported or no check;
  • Supports receiving/sending FIFO interrupt;
  • PDMA mode supported by UART1/3;
  • I2C
  • Supports standard speed, fast speed, and high speed modes;
  • Supports Master and Slave modes; 
  • SPI
  • Supports SPI standard 4-wire protocol;
  • Embedded independent 8x32 receive and send buffers;
  • Supports PDMA mode;
  • PWM
  • Supports preset frequency division;
  • 16-bit counting accuracy;
  • ADC
  • 6-channel analog inputs, 10bit accuracy; 
  • GPIO
  • Two GPIO controllers;
  • Independent pull-up resistor enable;
  • Selectable drive strength (2/4/8/24mA);
  • Supports configurable interrupt of each IO, edge or level triggered; 



Block Diagram

SC5864D.png